The present invention relates generally to PWM (pulse width modulation) circuits which generate a PWM output signal in response to an PWM input signal, and more particularly to such PWM circuits which generate a PWM output signal having a fixed frequency and a duty cycle that is the same as the duty cycle of the PWM input signal.
PWM circuits are widely used as control circuits, especially in electric motor driving applications. PWM output signals typically are generated by means of digital circuitry and associated system clock signals or by means of analog comparator circuitry. For a typical brushless DC (BLDC) motor controller, the system clock fsys ranges from roughly 1 MHz to 10 MHz, and the expected output PWM frequency fPWM ranges from roughly 20 kHz to 200 kHz, depending on the specific application.
One prior art PWM motor driving circuit includes a specially designed PWM generator, an output multiplexer (MUX), and an interpolator to increase duty cycle resolution. (The term “duty cycle resolution” refers to the smallest permissible increment or change in duty cycle in a system. For example, if a digital system can compute or provide an output duty cycle of 4% or 5% but can not compute or provide any fractional duty cycle resolution between 4% and 5%, then the duty cycle resolution in the system is 1%.) Another prior art technique for increasing duty cycle resolution is to use an RC filter to convert the duty cycle from PWM to a DC value, use an ADC (analog to digital converter) to convert the DC value of the duty cycle to a digital representation, and then digitally generate a PWM output signal with precisely the same duty cycle and precisely the same desired frequency. Yet another known method is to use a counter to determine a positive duty cycle duration and divide it by the total duty cycle to determine the duty cycle and use that information to generate a PWM output signal.
Some users of motor driver circuit circuits may prefer to provide relatively low PWM input signal frequencies, in the range from roughly 2 kilohertz to as high as roughly 100 kHz or higher. The user-provided PWM input signal ordinarily is applied directly to the motor driver circuit. The motor driver integrated circuit may require the motor driving PWM frequency to be a particular fixed frequency, but in some cases that may be unsuitable for the user. Instead, the user may want the motor driving PWM frequency to be independent of the frequency of the PWM input signal provided by the user. Some previous PWM circuits are able to meet this requirement. For example, a counter may be used to determine the positive pulse width and total pulse width of the PWM input signals, and a divider may be used to determine the duty cycle signal, which then is used by a PWM generator circuit to generate the PWM output signal.
In a typical motor system, the cycle-to-cycle PWM pulse width variations can be filtered out by the momentum of the physical rotor, which can be viewed as a low-pass filter system. However, in many cases users would like to use a low frequency PWM input signal to control the motor driver circuit, but unfortunately low frequency PWM signals generally are not suitable for driving an electric motor. Instead, many users would like to use a corresponding substantially higher frequency PWM output signal to drive the motor. If the PWM input signal has a relatively low frequency, the substantially higher frequency of the PWM output signal is typically achieved using the above mentioned counter and divider technique. Some traditional circuits require the input PWM frequency to be within a certain range, and some use a counter and divider converter as mentioned above. It is usually preferred that the frequency of the PWM motor driving signal be independent of the user-supplied PWM control signal frequency.
In many cases, it is undesirable for the motor speed controlled by a motor driver integrated circuit to either increase too rapidly or decrease too rapidly. When there is an abrupt increase of the duty cycle, the motor typically accelerates under application of full power. This may cause a large amount of current to be drawn from the power supply, and this may cause a sudden, large, and unacceptable decrease in the power supply voltage. Conversely, when there is an abrupt decrease of the duty cycle, the motor typically decelerates, by strongly “braking” the rotor. Such strong braking converts mechanical energy of the rotor to electrical energy which is rapidly “dumped” back into the power supply. Too much energy being dumped back into the power supply may cause a large spike in power supply voltage (e.g., from 5 volts to 10 volts), which could damage other circuits/devices in the system.
Thus, there is an unmet need for a PWM circuit which can generate a PWM output signal which has an output frequency that is independent of a user-supplied PWM input signal frequency, wherein the duty cycle of the PWM output signal is precisely equal to the duty cycle of the PWM input signal.
There also is an unmet need for a PWM circuit which can generate a relatively high frequency PWM output signal in response to a relatively low frequency PWM input signal independently of a user's PWM control signal frequency, wherein the duty cycle of the high frequency PWM output signal is precisely equal to the duty cycle of the low frequency PWM input signal.
There also is an unmet need for a PWM circuit which can generate a relatively high frequency PWM output signal in response to a relatively low frequency PWM input signal independently of a user's PWM control signal frequency, wherein the duty cycle of the high frequency PWM output signal is programmable, is exactly equal to the duty cycle of the low frequency PWM input signal, and has at least as much resolution as the duty cycle of the low frequency PWM input signal.
There also is an unmet need for a PWM duty cycle synthesizer circuit which can avoid causing abrupt transfer of energy between a power supply and a PWM-controlled electric motor due to a duty cycle difference between a PWM input signal and a duty cycle of a PWM output signal generated in response to the PWM input signal.
There also is an unmet need for a PWM duty cycle synthesizer circuit which can prevent the motor from abruptly causing rapid acceleration or deceleration of rotation in the motor due to duty cycle mismatch between the PWM input signal and the PWM output signal.
There also is an unmet need for a PWM circuit which can generate a PWM output signal having a first frequency in response to a PWM input signal having a second frequency independently of a user-supplied PWM control signal frequency, wherein the duty cycle of the PWM output signal is precisely equal to the duty cycle of the PWM input signal, and wherein the PWM circuit response time to a step change in the duty cycle is programmable.
There also is an unmet need for a PWM circuit which can generate a PWM output signal having a first frequency in response to a PWM input signal having a second frequency independently of a user-supplied PWM control signal frequency, wherein the duty cycle of the PWM output signal is precisely equal to the duty cycle of the PWM input signal, and wherein the PWM circuit can be implemented in substantially less integrated circuit chip area than the closest prior art.